In digital data systems in general, and in computer systems in particular, there is an ever-increasing drive for larger bandwidth and higher performance. These systems are comprised of discreet integrated circuit chips that arc interconnected. Data moves through a chip and between chips in response to clock pulses, which are intended to maintain synchronization of the data in parallel paths. At the extremely high data rates in today's systems, variations in the propagation of data over a bus along one path as compared to another path on the bus (i.e. skew) can exceed one clock cycle. U.S. Pat. No. 6,334,163, which is assigned to the assignee of this application and is incorporated herein by reference, discloses a so called Elastic Interface (EI) that can compensate for bus skew greater than one clock cycle without a performance penalty. However, packaging technology has not been able scale up to match the performance and bandwidth of the chip and interface technologies. In order to reduce the number I/O terminals on a chip and the number of conductive paths in a bus between chips, the prior art transfers data at a so called Double Data Rate (DDR), in which data is launched onto the bus at both the rising and falling edges of the clock. This allows the same amount of data to be transferred (i.e. bandwidth) with only half the number of bus conductors and half the number of I/O ports, as compared with a system where data is transferred only on a rising or a falling edge. The higher frequency employed in a Double Data Rate bus requires a finer granularity in capturing data at the receiver end of the bus. This requires an increase in the number of latches in an elastic interface in order to maintain the same elasticity interval as compared with a bus operating at a lower frequency. For example, if there were four clock cycles of elasticity at a data transfer rate of x, going to a double data rate mode of data transfer doubles the number of receiver latches that may be required to maintain the same elasticity. This decreases the time duration of valid data being kept by the receiving logic, thus forcing the receiver to have more logic and storage circuits to yield the same valid data time. The receiver logic and storage circuits are especially important and become complicated when the packaging cannot force wire to de-skew arriving data among chip interfaces and all data is required to arrive at the receiving end on the same logical cycle.
It is also common and necessary to partition and transfer instructions and data signals across multiple integrated circuit chips. One of the requirements is that the signals at the receiving ends of one or multiple chips must be synchronized in the same cycle. Even though the driver chips send signals in the same cycle, the signals arrive at the receiver chip(s) not necessarily in the same cycle due to delay differences of the transmission lines of high-speed interfaces. To meet this receiver synchronization requirement, the receiver chip utilizes complicated logic and/or circuit techniques to resynchronize the signals back to the same cycle to compensate the delay differences. Due to the high computer clock frequency and data transfer rate, the signal delay differences from different driver chips are multiple cycles at the receiver chip(s). The multi-cycle delay differences can often be beyond the limit that the receiver chip(s) being able to compensate.